1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a synchronous type memory for controlling the execution of instructions.
2. Description of Related Art
In recent years, a high-speed handling, energy saving and compact size are in strong demand for the semiconductor integrated circuits.
FIG. 1 is a block diagram showing the structure of a semiconductor integrated circuit having a synchronous type memory division, which is disclosed in Japanese Patent Application Laid-Open No. 2-172094 (1990). The synchronous type memory division 4 includes a two-port RAM, and executes the performances of precharging bit lines, driving word lines, and operating a sense amplifier in each machine cycle by using a four-phase clock generated by an all-purpose acoustic signal processor. A first control circuit 1 is provided for each bit line for a first address signal address AD1, and the first address signal AD1 and a first synchronizing signal SS10 and a second synchronizing signal SS20 are inputted to the control circuit 1.
The second synchronizing signal SS20 is also inputted to one of the input terminals of an AND gate 2. The first control signal SC1 outputted from any of the control circuits 1 is inputted to an OR gate 3 having several input terminals as part of the second control circuit, and the output thereof is inputted to the other input terminal of the AND gate 2 as part of the second control circuit. The second control signal SC2 outputted from the AND gate 2 is inputted to the synchronous type memory division 4 which outputs a data DT. The second address signal AD2 outputted from the control circuit 1 is inputted to the synchronous type memory division 4. This prior art semiconductor integrated circuit does not read a series of data and continues to output an output data for the address signals if the address signal inputted remains the same throughout several machine cycles.
FIG. 2 is a circuit diagram showing the internal structure of the control circuit 1. There are connected a first register 5, a second register 6, and a third register 7 and an XOR gate 8. The first register 5 receives the first synchronizing signal SS10 and the first address signal AD1, and outputs signals to one of the input terminals of the second register 6 and XOR gate 8. The second register 6 receives the second synchronizing signal SS20, and outputs a second address signal AD2 which is then inputted to the third register 7. The third register 7 receives the first synchronizing signal SS1O and the second address signal AD2, and outputs a signal to the other input terminal of the XOR gate 8 which outputs the first control signal SC1.
FIG. 3 is a block diagram showing the internal structure of the synchronous type memory division 4 of FIG. 1. The synchronous type memory division 4 includes an X decoder 9, a Y decoder 10, a Y selector 11, a bit-line precharging circuit 50, a memory cell array 12 and an output circuit 13. Each bit of the second address signal AD 2 is inputted to the X decoder 9 and the Y decoder 10. The second control signal SC2 is inputted to the X decoder 9 and the bit-line precharging circuit 50 which is connected to the memory cell array 12 through each bit line BL. The X decoder 9 is connected to the memory cell array 12 through each word line WL. The Y selector 11 is connected to the memory cell array 12 through each bit line BL. The Y decoder 10 inputs a decoding signal SDC to the Y selector 11. The Y selector 11 is also connected to the output circuit 13 which outputs an output data DT.
The semiconductor integrated circuit is operated as follows:
The first address signal AD1 is held by the first register 5, and the data held by the first register 5 is held by the second register 6 synchronously with the second synchronizing signal SS20. The data in the second register 6 is held by the third register 7 synchronously with the first synchronizing signal SS10. The data in the second register 6 is outputted as the second address signal AD2. The data in the first register 5 and in the third register 7, that is, the data held by the first register 5 one cycle before establish an exclusive-or operation at the XOR gate 8, and the XOR gate 8 outputs the first control signal SC1 representing that the addresses in the present cycle and the previous (one cycle before) cycle are in agreement or not. At this stage, the first control signal SC1 becomes H-level when discord is found in data, and becomes L-level when accord is found in data. The first control signal SC1 from one of the control circuits 1 is inputted to the OR gate 3, and the second synchronizing signal SS20 and an output from the 0R gate 3 establish a logical sum of the AND gate 2. As a result, only when the first address signal AD1 is different between the present cycle and the previous (one cycle before) cycle, the second control signal SC2 is inputted to the synchronous type memory division 4 synchronously with the second synchronizing signal SS20. The second address signal AD2 outputted from one of the control circuits 1 is directly inputted to the synchronous type memory division 4. The synchronous type memory division 4 reads a series of data only when the second control signal SC2 synchronous with the synchronizing signal SS20 is inputted (at H-level), thereby keeping the first address signal AD1 unchanged. This means that when the second control signal SC2 is at L-level, no data is read from the synchronous type memory division 4.
FIG. 4 is a diagram showing the operations of signals within the synchronous type memory division 4. Machine cycles are designated by MO, M1 through M5 which divides the operation of the synchronous type memory division 4 event by event. The second address signal AD2 to be inputted to the synchronous type memory division 4, that is, the data in the second register 6 changes with each machine cycle MO, M1, M4 and M5, and does not change in the machine cycles M2, M3 and M4. The first control signal SC1, which represents the accord and discord between the data held in the present cycle and in the previous (one cycle before) cycle, becomes L-level synchronously with the first synchronizing signal SS1O in the machine cycle M2, and becomes H-level synchronously with the first synchronizing signal SS1O in the machine cycle M4. The second control signal SC2, which is a synchronizing signal of the synchronous type memory division 4, is maintained at L-level during the period of time from the machine cycles M3 to M4, so that during this period of time the electric potential of the bit lines BL and the word lines WL remains the same and continue to output the data (D) or (C) in the machine cycle M2. As a result, during the machine cycles M3 and M4, the synchronous type memory division 4 does not read a series of data for precharging the bit lines BL, driving the word lines WL, discharging the bit lines, and operating a sense amplifier.
The aforementioned are the operations of reading data followed by the synchronous type memory division 4, and the same operations are followed when data is written.
The known semiconductor integrated circuit has the structure described above, and if electricity is to be saved by prohibiting the reading of a series of data which would otherwise be performed by the synchronous type memory division, a special arrangement is required for effecting the comparison of addresses. More specifically, each bit requires a three-stage of address registers to hold memory addresses, and a comparator is additionally required to compare the outputs of the first register 5 and third register 7, thereby resulting in an increased number of hardwares in the circuit. As a result, the production cost is increased and the chip area becomes enlarged against the expected ideal of compact size.
There is a data processor such as a microprocessor utilizing a pipe line structure which is equipped with the synchronous type memory division in the instruction execution control division, that is, a .mu. ROM. This type of known device has the following disadvantages:
However, the address comparison system referred to above is not effective to save electric current for the following reasons:
For example, an instruction fetch stage (hereinafter referred to as "IF stage"), a decoding stage (hereinafter referred to as "D stage"), a .mu.-code reading stage (hereinafter referred to as "R stage"), and an execution stage (hereinafter referred to as "E stage") are constructed in this order. These stages are operated in parallel. In this pipe line structure, when a branch instruction is to be executed, it is in the D stage when it is found to be a branch instruction, and when this instruction is decoded, an instruction following the branch instruction (which invalidates the operation in the pipe line) is fetched from an external memory in parallel in the IF fetch stage. This invalid instruction is specially prohibited from performing in the E stage, wherein the "special prohibition" means that if, for example, it is an instruction for directing the writing of data in the register, a prohibiting signal is delivered to the E stage so as to prevent the writing of data into the register. However, in the synchronous type memory division in the R stage the reading of data from the .mu. ROM is nevertheless performed on the basis of the invalid instruction, thereby wasting electricity in reading data from the .mu. ROM.